Elemental Ge exhibits many device advantages over pure Si. Its smaller bandgap is attractive for photodetector and modulator applications in the 1.3-1.6 μm wavelength range (see, Oh et al., IEEE J. Quantum Electron. 38, 1238 (2002); Liu et al., Appl. Phys. Lett. 87, 103501 (2005); and Kuo et al., Nature 437, 1334 (2005)). Transistors based on Ge should also provide greater speed performance due to higher carrier mobilities of this material. Since the manufacturing infrastructure for Si—Ge technologies is well established, the direct growth of Ge on Si could produce new classes of opto- and microelectronic systems, but such growth has been problematic. The conventional formation of mismatched (4%) Ge on Si typically proceeds via the Stranski-Krastanov mechanism yielding islands (after deposition of 3-4 monolayers) rather than relaxed, continuous layers. For thick films a high roughness is obtained and threading dislocation densities of ˜108 cm−2 are commonly observed (see, Kroemer et al., J. Cryst. Growth 95, 96 (1989)). Carrier scattering and traps at defect sites reduce mobility in electronic devices and also increase dark current in photodetectors.
Low temperature (T<375° C.) chemical vapor deposition (CVD) of GeH4 has produced Ge layers directly on Si(100) possessing fairly smooth surfaces with occasional pits, and threading dislocation densities that appear to be too high for certain applications (see, Cunningham et al., Appl. Phys. Lett. 59, 3574 (1991)). Higher temperature growth (T>400° C.) invariably produces rougher layers that display the classic cross-hatched patterns created by strain relaxation and defect formation. The higher temperatures also increase the propensity of microcrack formation upon cooling of the samples (see, for example, Currie et al., Appl. Phys. Lett. 72, 1718 (1998); and Fitzgerald et al., J. Vac. Sci. Technol. B 10, 1807 (1992)) making such approaches incompatible with back end (post-metallization) CMOS processes. A more recent method utilizes thick graded buffers of Si1-xGex in which the Ge content is gradually increased up to 100% to relieve the misfit strain with the substrate. Typically 10 μm is required to achieve acceptable levels of threading defects (˜106 cm−2) and a complicated chemical mechanical polishing step is necessary to produce a smooth surface, making device processing expensive (see, Luan et al., Appl. Phys. Lett. 75, 2909 (1999)).
Growth of Ge on Si typically proceeds via the Stranski-Krastanov mechanism, yielding islands (after deposition of 3-4 monolayers) rather than relaxed, continuous layers. For thick films a high roughness is obtained and threading dislocation densities of ˜108 cm−2 are commonly observed, eventually producing the classic crosshatched surface morphologies (see, Fitzgerald and Samavedam, Thin Solid Films, 1997, 294, 3). Scattering and traps at defect sites reduce carrier mobility in electronic devices and also increase dark current in photodetectors. A variety of growth schemes have been developed in an attempt to circumvent some of these problems, including (i) the use of a graded Si—Ge buffer layer (see, Fitzgerald and Samavedam, supra), (ii) a two-step growth in which an initial thin buffer layer is deposited at low temperature, followed by the high temperature growth of the bulk material (see, Luan et al., supra), and (iii) surfactant-mediated epitaxy using As and Sb atomic beams (see, Wietler et al., Appl. Phys. Lett. 2005, 87, 182102). The compositionally graded Si1-xGex buffer layer approach has been demonstrated via UHV-CVD. The Ge concentration is gradually increased as a function of layer thickness, and the terminal Ge portion of the stack exhibits a defect density of 107 cm−2 and a high AFM RMS roughness of 50 nm. A post growth chemical mechanical polishing step is then conducted to reduce the surface roughness to a level that allows subsequent growth of lower defect density overlayers of the Ge material. The drawbacks of this method include excessive final film thicknesses (˜11 μm) and a relatively large residual surface roughness, both of which are problematic for device fabrication. An alternative two-step UHV-CVD process has also been developed (current state-of-the-art) to produce relaxed Ge on Si films with relatively flat surfaces. Here an initiation layer of ˜50 nm in thickness is first grown at low temperatures of ˜350° C. This layer is intended to facilitate subsequent bulk growth at higher temperatures ˜800-900° C. and significantly enhanced rates. In this process the excess hydrogen on the growth surface is believed to act as a surfactant, thereby promoting the formation of misfit dislocations parallel to the Ge/Si interface which relieve the misfit strain. The surface morphology of the resultant films reveals an AFM RMS roughness value of 0.5 nm with no sign of the crosshatch pattern attributed to strain relaxations. However, defect densities of 2.3×107 cm−2 are purportedly present even after thermal cycling of the samples between 780-900° C. Further reductions in defect densities to levels as low as ˜2×106 cm−2 can be obtained using this method via selective growth on oxide patterned Si wafers (see, Fitzgerald and Samavedam, supra). In recent years more conventional surfactant-based approaches have been implemented via MBE to grow Ge layers with suitable morphologies using solid sources of As or Sb. This is typically achieved by first depositing a completed surfactant monolayer on clean Si prior to growth of pure Ge. Using this method ˜1 μm Ge thick films with defect densities of ˜2×107 have been demonstrated at 700° C. (the surface roughness was not reported in this case; see, Wietler et al., supra). The resultant films have been found to exhibit tensile strains as high as 0.2% due to the thermal mismatch with the Si substrate. They are also unintentionally doped by the As/Sb surfactant.
These issues have prompted us to consider an alternative, more straightforward approach which obviates the need for thick buffers and associated processing problems.